1. Field
Embodiments of the invention relate to electronic systems, and more particularly, to signal input/output (IO) protection devices referenced to a single power supply.
2. Description of the Related Technology
Certain electronic systems can be exposed to a transient electrical event, or an electrical signal of a relatively short duration having rapidly changing voltage and high power. Transient electrical events can include, for example, electrical overstress (EOS) such as electrostatic discharge (ESD) events.
Transient electrical events can damage integrated circuits (ICs) inside an electronic system due to overvoltage conditions and/or high levels of power dissipation over relatively small areas of the ICs. High power dissipation can increase IC temperature, and can lead to numerous problems, such as thin gate oxide punch-through, shallow junction damage, narrow metal damage, and surface charge accumulation.
Moreover, relatively large scale System-on-a-Chip (SoC) for multi-Gigabits/second communication can integrate distributed and multi-level data conversion functionality on an integrated circuit. Such a system can use process technologies such as complementary-metal-oxide-semiconductor (CMOS) technologies that combine a large digital signal processing unit with high speed analog circuits utilizing supply voltages in the range of, for example, about 0.9 V to about 3 V. System interfaces are often required to have the capability of handling signals referenced to power low, for instance, ground GND, and that go beyond power high, for instance, a high supply voltage VDD, or vice-versa. Under this constraint, the TO protection devices need to provide robust protection with reference to a single supply. Large-scale functionality SoC are particularly prone to fail during manufacturing due to complexity involved in implementing unconventional distributed on-chip protection against electrical overstress without degrading signal integrity. The damage can be caused by overstress such as charged-device-model (CDM) ESD stress conditions, affecting the yield and viability of the reliable system implementation.
There is a need to provide effective protection devices, including protection devices suitable for interface pins allowed to have reference to a single supply for relatively large scale System-on-a-Chip (SoC) applications.